Experimental data going back two decades have shown the distribution of delay-related failures is skewed toward small delays. That is, the majority of devices that fail due to delay defects fail because of “small delay defects.” Small delay defects contribute to delays shorter than the clock cycles associated with the design and process technology node. As design sizes and performance continue to increase, more and more designs will be susceptible to small delay defects. Detecting and isolating small delay defects, therefore, have attracted considerable effort in the VLSI (very-large-scale integration) test community.
Two main fault models have been developed for timing related defects. The transition delay fault model is commonly used by ATPG (automatic test pattern generation) tools to target timing related defects, whereby the conditions for detection are that a transition has occurred on the node, and the logic effect of that transition has been propagated to and captured by a scan cell. Detection of a transition fault is generally independent of which path is used to sensitize and propagate the fault because it assumes that a delay defect causes a delay longer than one clock cycle. Many ATPG tools, optimized to minimize run time and pattern counts, tend to generate tests using shorter paths rather than longer ones. Consequently, some small delay defects may not be detected when the paths activated are too short for any delay effects to be observed at a scan cell.
The path delay fault model is also used for at-speed scan testing. This model tests the cumulative effect of all delays along a specific path. Unfortunately, the number of paths as a function of circuit size can grow exponentially, and it is therefore only practical to target a limited number of critical paths with this fault model. Because the tested paths are usually a very small fraction of the paths in the design that can be targeted, only those small delay defects along the tested paths may be detected.
Even after small delay defects are detected, isolating and identifying these defects remain challenging. Small delay defects usually cause much fewer failures on a tester since not all paths can lead to failures at scan cells as explained above. As such, each failure captured may be associated with a large number of defect suspects, leading to low diagnosis resolutions. While timing information from a logical or physical design may be used to improve diagnosis resolutions, the timing information is often insufficient as many small delay defects are caused by manufacturing process variations.
FIG. 1 illustrates some of the diagnosis challenges. It can be assumed that a small delay defect 110 at the output of gate m in the circuit causes a failure that can only be propagated along the longest path 120 and exhibits the fault effect at observation point a 130. It also can be assumed that only one test pattern activates this longest path during the production test and causes a single failure at observation point a 130. Since there is only a single failing bit, the diagnosis report usually contains multiple suspects (the gates' inputs and outputs that might cause the failure at point a 130). In this example, the input and output of all the gates in the figure {f, g, h, i, j, k, m} may be reported as diagnosis suspects. On the other hand, if the defect at the output of gate m is of normal and large size, many paths passing through m may lead to multiple failing bits and thus the list of diagnosis suspects should be considerably shorter. Thus, it is more difficult to pinpoint and locate small delay defects. Note that failing bits, failing scan cells and failing observation points are used herein interchangeably.
In general, there are two approaches to diagnosis. The first is to develop an algorithm for a particular fault model, such as transition delay and path delay fault models. These algorithms may target single- or multiple-fault locations. For example, fault simulation based on SLAT (single location at a time) has been developed for multiple defects. The second approach to diagnosis is to create a fault dictionary upfront. This fault dictionary stores signatures of all potential faults in a circuit. When a chip fails on a tester, the failure on the tester is compared to the fault signature entries stored in the fault dictionary, and the fault signature that best matches the tester failure will be treated as the best defect suspect. While both approaches work well, the diagnosis resolution sometimes is limited by production test patterns or the number of failures collected on a tester. In order to achieve higher diagnosis resolution before the more expensive physical fault isolation process, diagnostic test pattern generation (DTPG) techniques is usually used. DTPG techniques can be used with either of the two diagnosis approaches described above.
A number of DTPG methods have been developed. In T. Bartenstein, “Fault Distinguishing Pattern Generation”, Proc. ITC, 2000, pp. 820-828, which is incorporated herein by reference, each pattern in a diagnostic test pattern set is used to distinguish a pair of suspect defects. In another words, for each pair of suspects (e.g. m and j in FIG. 1), the diagnostic test generation usually tries to activate and propagate one suspect without activating or propagating the other one. In Z. Wang, et al., “Multiple Fault Diagnosis using N-detection Tests”, Proc. ICCD, 2003, pp. 198-201, which is incorporated herein by reference, each suspect is detected by n different test patterns. The n different test patterns are test patterns that can activate and propagate the faulty effect of the suspect along different paths. Neither method, however, is designed to target small delay defects. Accordingly, some small delay defects may be missed when none of the long paths required for detecting these small delay defects are activated by the test pattern set generated. Several other methods apply timing information to guide diagnostic test pattern generation. As already mentioned, the timing information and static timing analysis might be insufficient for diagnosing small delay defects due to timing model inaccuracy and manufacturing process variations.